CNN Central News & Network-ITDC India Epress/ITDC News Bhopal: India has achieved its target of preparing 85,000 semiconductor engineers in four years against a 10-year goal: Ashwini Vaishnaw.
Nearly 10 percent of the global semiconductor industry market will be in India in the coming years: Ashwini Vaishnaw.
Students from Tier-2 and Tier-3 cities have designed more than 250 semiconductor chips: Ashwini Vaishnaw.
Jabalpur. Union Minister for Electronics and Information Technology, Railways, and Information and Broadcasting Shri Ashwini Vaishnaw today addressed the media and outlined the government’s vision for taking India’s semiconductor ecosystem to the next level. On the occasion, notifications were issued for all six pillars of the Semicon 2.0 scheme, marking an important step towards strengthening India’s semiconductor design and manufacturing capabilities.
The scheme builds on the momentum gained from the first Semicon India programme and provides financial and infrastructure support across the semiconductor value chain, from chip design, fabrication and packaging to equipment, materials, research and development, and talent development.
The scheme aims to strengthen India’s economic growth and national security by enhancing the resilience of the semiconductor supply chain and establishing technological leadership in critical sectors. It will operate through six pillars covering 10 categories.
The six main pillars under Semicon 2.0 are:
Pillar 1 – Design
Pillar 2 – Machines and materials
Pillar 3 – Establishing more fabs
Pillar 4 – Further strengthening the ATMP/OSAT industry
Pillar 5 – Research and development
Pillar 6 – Talent development
Pillar 1 – Design: Categories: design of semiconductor IP, chips, system-on-chip (SoC) and modules for national importance and strategic priorities; design of semiconductor IP, chips and SoCs for the commercial sector; and deployment-linked incentives (DLI) for semiconductor IP/chips/SoCs for deployment.
Pillar 2 – Machines and materials: Category: semiconductor manufacturing ecosystem.
Pillar 3 – Establishing more fabs: Categories: silicon semiconductor wafer fab; compound semiconductor/photonics/sensors (including MEMS) fab/discrete semiconductor fab; and display fab.
Pillar 4 – Further strengthening the ATMP/OSAT industry: Category: semiconductor assembly, testing, marking and packaging (ATMP) / outsourced semiconductor assembly and test (OSAT) facility.
Pillar 5 – Research and development: Category: research and development for advanced semiconductor technologies.
Pillar 6 – Talent development: Category: talent development.
During the programme, Shri Ashwini Vaishnaw said, “India has achieved its target of preparing 85,000 semiconductor engineers in 10 years in just four years, and has now set a new target of preparing one lakh more engineers. In the coming years, nearly 10 percent of the global semiconductor industry market is expected to be in India. Students from Tier-2 and Tier-3 cities have already designed more than 250 chips. In one case, commercial production began within just 13 months of the foundation stone being laid, while in several cases approvals were granted within 200 days, 150 days and even 90 days. The semiconductor ecosystem developing in India is also expected to create 50,000-60,000 direct jobs.”
Projects supported under Semicon 2.0 will generally have a duration of up to six years, while the scheme will initially remain open for applications for three years.
The India Semiconductor Mission (ISM) will be the nodal agency for Semicon 2.0. It will invite applications, carry out technical and financial evaluation, recommend applicants and oversee implementation. ISM may implement the design and deployment categories with the assistance of C-DAC. The mission may also announce semiconductor deep-tech awards from 2026 to promote specific innovation.
The Ministry of Electronics and Information Technology will make budgetary provisions for financial support, and payments will be made as per the conditions approved by the nodal agency. A mid-term evaluation will be carried out after three years of implementation of the scheme, or as required, to assess its impact and consider amendments or continuation.
Hashtags: #MadhyaPradesh #Bhopal #Jabalpur #AshwiniVaishnaw #Semicon2 #Semiconductor #IndiaSemiconductorMission #Semicon20 #SemiconductorEngineers #ChipDesign
